Joe Ganley's Biography

Professional

I grew up in Arlington, Virginia. I got a B.S. and M.S. in Computer Science from Virginia Tech. While there, I (among other things, of course) was on their ACM Programming Team for two years. We placed third in the world in 1991 (my name was then Joe Lavinus [1]). Among the projects I worked on during my undergraduate years was a tool for extracting software quality metrics from code written in any of a number of languages (similar to the tools offered by McCabe and Associates), and a 3-D wireframe modeling tool that fed into a friend's ray-tracer.

During my Master's, I first worked with Adrienne Bloss on implementation issues involved in doing heavy numerical computations in purely functional languages such as Haskell. Dr. Bloss left in the middle of my time there, so I then did my thesis with Lenwood Heath. The topic was organizing object-oriented databases on slow-access media such as CD-ROM so that they can be accessed rapidly under various access models (searching, browsing, etc.). This was part of the Envision project, and I wrote several papers on this work.

In the summer between the first and second years of my M.S., I worked at the United States Postal Service Research Center. I worked on optical character recognition (implementing in software, and ultimately improving, the OCR algorithm implemented by the USPS sorting hardware) and on image compression (the goal was to find compression algorithms with good compression ratios, but such that OCR could be performed directly on the compressed images).

I then got a Ph.D. in Computer Science from the University of Virginia. My advisor was James Cohoon, and my topic was algorithms for physical design of integrated circuits (the same thing I work on now, amazingly enough). Specifically, I examined a number of variations on the Steiner tree problem (for a time, I was one of the world's leading authorities on Steiner tree problems), and I designed and implemented a Steiner-tree-based placement and routing tool for field-programmable gate arrays. I wrote many papers on this work. My dissertation was nominated for both the ACM and SIAM doctoral dissertation awards. I was also awarded a Virginia Space Grant Fellowship and a University of Virginia Dean's Fellowship.

Upon finishing my Ph.D., I went to work for Cadence Design Systems in San Jose, California. I worked in San Jose for about two years, and then for another two as a full-time telecommuter from my home in Virginia. The primary product on which I worked was Virtuoso XL (formerly known as the Device-Level Editor). I also worked on the Virtuoso Layout Editor, which has since been subsumed by Virtuoso XL. Virtuoso itself is an editor for the physical layout of an integrated circuit -- what we in the business refer to as a "polygon pusher." You can think of this as a very powerful, complex drawing program that understands electricity. Virtuoso XL runs atop Virtuoso, and aids users in transforming the symbolic representation of a circuit (e.g. a schematic or netlist) into a physical layout, and in maintaining the correspondence between them during edits to either the schematic/netlist or the layout (or both). Virtuoso XL also adds a number of additional advanced editing features to Virtuoso.

Among the specific projects on which I worked at Cadence:

I entirely rewrote the layout generation system in Virtuoso XL 4.4.3. This code creates, from a schematic, a functionally equivalent physical layout. It also maintains the correspondence between schematic and layout objects during editing of the schematic, the layout, or both.
I was the principal designer and sole developer for the first release of the Device-Level Placer (DLP) product. DLP computes a good physical arrangement of a set of devices in an integrated circuit layout, so as to minimize the length of the wires needed to interconnect them, and as to satisfy various user-specified geometric constraints (positions, alignment, symmetry, etc.). I completed DLP ahead of schedule with a superset of planned functionality. We published a paper at the CICC conference on DLP.
I wrote the first version of "guided path," an interactive, single-layer router.
I wrote the code for evaluating parameters and transforming them from schematic to layout and vice-versa in versions 4.4dd through 4.4.2. This code was replaced by the layout generation system rewrite described above.
Many, many more new features and bug fixes in Virtuoso XL, Virtuoso, the pCell compiler, etc.

At Cadence, I received an Engineering Special Achievement Award, a Cadence Quality Award (and was nominated for a second one), and a variety of smaller recognitions.

I left Cadence to work for Simplex Solutions, who was bought several years later by Cadence.

Personal

Name's the same:

There's a big chain of Ganley car dealers in Ohio; see Ganley Auto's website.
Ganley's Flowers.
I found Ganley International in whois; I have no idea what they do (site under construction).
There's another Joe Ganley who is a sports columnist for the Syracuse Herald-Journal.
There's a Ganley Mountain in Colorado, according to the USGS, but I skied at Arapahoe Basin and Keystone, both nearby, and none of the locals had ever heard of it.

Here's a picture of me with a beard - first (and if Cathy has her say, last) time I've ever grown one.